The present invention relates to data communication systems, and more particularly to header error detection and correction of ATM cells where a low processing delay is required.
ATM is an asynchronous data transmission system that transports data as cells of 53-bytes. Each ATM cell has a five-byte header having four bytes of information and a header error checksum ("HEC") of one byte followed by a payload of 48 bytes of data. The payload of 48 bytes, bytes 6 to 53, is for transporting a variety of telecommunication services, such as voice service, video service, internet services and similar services. Because SONET systems are becoming available for transmitting data at rates of 2488.32 Mb/s and above, there is a need for a low delay, high throughput ATM cell processor. Details of a SONET PATH/ATM PHYSICAL LAYER TRANSMIT/RECEIVE PROCESSOR related to the present invention are described in an earlier application by the assignee having Ser. No. 08/736,074 filed by the applicant on Oct. 25, 1996. In order for ATM cell transfers to operate efficiently with a SONET based system or other high-speed transmission system it is essential to have a low ATM cell processing time at nodes of the network.
In an ATM network the payload information content processing is provided by the end users after the ATM cell has been delivered. Hence the processing parameter of concern is the time required to process the header of the ATM cell. The information bytes of the header must be error free, since the information bytes contain the routing information for the ATM cell. In order to maintain the integrity of the information bytes a one byte header error checksum ("HEC") is generated using a specified generator polynomial as contained in the ITU Recommendation, I.432. The HEC is used to determine header integrity; i.e., if no errors have occurred, if one error has occurred, or if multiple errors have occurred. Further, if one error has occurred the HEC may be used to correct the error. Cells with error-free or corrected headers may be transmitted further, cells with headers containing multiple errors are dropped.
When the transfer data rates in an ATM network were in the 155 to 800 Mb/s range, a sequential processor was capable of the throughput necessary for processing the header. As transfer speeds increase to OC-48 SONET rates and above (2.5 Gb/s and faster), an improved processing apparatus is needed. The need for a cost effective circuit having maximum throughput has resulted in a novel apparatus for providing a low delay time error correction circuit as described below.